Shirt a Phobia

Sample Page

ERC32 is a radiation-tolerant 32-bit RISC processor (SPARC V7 specification) developed for space applications.[1][2][3] It was developed by Temic,[3] which was later acquired by Atmel,[4][5] and then Microchip.[6]

It is used in the DMS-R (Data Management System – Russian) computer of ‘Zvezda‘ section of the Russian Orbital Segment on the International Space Station (ISS). It is also used in the control, mission and failure management systems in the Russian segment, as well as the fault-tolerant systems of the Automated Transfer Vehicle and standard payload computer of the wider ISS.[7]

Versions

Two versions have been manufactured:[2][5]

  • ERC32 Chip Set (Part Names: TSC691, TSC692, TSC693)
  • ERC32 Single Chip (Part Name: TSC695, TSC695F)

Support

Support for the chip set version of the ERC32 has been discontinued.[2] ERC32 was succeeded by LEON (SPARC V8 specification).[8][9]

References

  1. ^ Corbière, T.; Gaisler, J. (July 1997). Kaldeich-Schürmann, Brigitte (ed.). ERC 32 Radiation Tolerant RISC Processor; Tolerance to Radiation. Electronic Component Conference – EECC’97, Proceedings of the 3rd ESA Electronic Component Conference held 22-25 April, 1997 at ESTEC, Noordwijk, the Netherlands. Paris: European Space Agency. Bibcode:1997ESASP.395..475C. Retrieved 23 March 2026 – via SAO/NASA Astrophysics Data System.
  2. ^ a b c “ERC32”. European Space Research and Technology Centre. 31 October 2011. Retrieved 23 March 2026.
  3. ^ a b Gorbunov, M.S. (11 April 2019). “Design of fault-tolerant microprocessors for space applications”. Acta Astronautica. 163 (Part A) (published October 2019). doi:10.1016/j.actaastro.2019.04.029. Retrieved 23 March 2026 – via Science Direct. The first chip was SPARC V7 ERC32 32-bit microprocessor designed by Gaisler Research AB (now Cobham Gaisler AB) and manufactured by Temic GmbH (now Atmel).
  4. ^ “Atmel Acquires Temic Semiconductor’s Integrated Circuit Business”. EE Times. 9 March 1998. Retrieved 23 March 2026.
  5. ^ a b Renaud, Nicolas (6 September 2005) [6-8 July 2005]. How to Cope with SEU/SET at Chip Level? The Example of a Microprocessor Family. 11th IEEE International On-Line Testing Symposium. Institute of Electrical and Electronics Engineers. p. 313. doi:10.1109/IOLTS.2005.33. ISBN 0-7695-2406-0. ISSN 1530-1591. Retrieved 23 March 2026 – via IEEE Xplore. …a SPARC processor product line for space has been made available by ATMEL since now more than ten years, starting by the ERC32 three chips processor and followed by the TSC695F ERC32 single chip processor.
  6. ^ “Microchip Technology completes Atmel acquisition”. Reuters. 4 April 2016. Retrieved 23 March 2026.
  7. ^ Pouponnot, A.L.R. (6 September 2005) [6-8 July 2005]. Strategic use of SEE mitigation techniques for the development of the ESA microprocessors: past, present, and future. 11th IEEE International On-Line Testing Symposium. p. 320. doi:10.1109/IOLTS.2005.66. ISBN 0-7695-2406-0. ISSN 1942-9401. Retrieved 23 March 2026 – via IEEE Xplore.
  8. ^ “Overview of LEON tools”. European Space Agency. 11 November 2009. Retrieved 23 March 2026. The LEON is ERC32’s successor and is the latest iteration of ESA’s effort in providing a source of radiation tolerant microprocessors to the European space industry.
  9. ^ Parra, Pablo; da Silva, Antonio; Losa, Borja; Ignacio García, J.; Rodríguez Polo, Óscar; Martínez, Agustín; Sánchez, Sebastián (24 July 2023). “Tailor-made Virtualization Monitor Design for CPU Virtualization on LEON Processors”. ACM Transactions on Embedded Computing Systems. 22 (4) 60. Association for Computing Machinery: 5. doi:10.1145/358470. eISSN 1558-3465. Retrieved 23 March 2026. LEON is an implementation of the SPARC V8 architecture whose development was promoted by the ESA as an evolution of the ERC32 platform.